1. Field of the Invention
This invention relates to an integrated circuit device which is able to test connections of an internal circuit even if it has a number of external pins.
2. Description of Related Art
Conventionally, particularly in logic LSI (Large Scale Integrated Circuit), in order to simplify the circuit functions test, it has been prevalent that the scantest circuit, which is a dedicated circuit for the testing, is arranged in the LSI, and the test is performed according to the scan path technique to check if the combination circuits are properly operating.
This scantest circuit is configured with the scan path chain in which the scan flip-flops are connected in series and operates as a shift resistor. The scan test circuit comprises scan-in pins, a scan-clock pin and scan-out pins. The scan-in pin is for inputting scan-in signal that is the data for scantest (scantest pattern) from outside or inside the LSI, the scan-clock pin is for inputting the clock from outside the LSI for scan path test, and the scan-out pin is for outputting the output data of the scantest that is the result of the scantest.
In the scan path technique, during test mode (shift mode), the scantest pattern for the test is supplied via the scan-in pins (hereafter, referred to as “scan-in”), and the scan-clock for the test is supplied to the clock pin. Then, the scantest pattern is logic-computed by the combination circuit in the LSI to output, from the scan-out pins, the result of the computation as a scantest output data (hereafter, referred to as “scan-out”). By comparing the outputted data with the predetermined expected value to check whether or not they are equal, it is possible to see if the combination circuit is properly operating. That is, if the scanned-out outputted data matches the pre-calculated projection value, it is determined that there is no defect in the combination circuit. If not, it is determined that there is a manufacturing defect. In this manner, by employing the scantest circuit, the inside of the circuit can be separated as a combination circuit, so that the testing can be simplified.
By the way, in such a test of LSI, if the number of the external signals (external pins) of the LSI is greater than that of the signals of the tester (test pins) for the testing, the new tester having more test pins (hereafter, referred to as “high-number-pins tester”) is usually employed. But, employing this high-number-pins tester requires installation of additional new equipment. In addition, the high-number-pins tester is of extremely expensive device.
As an example of such a method, Japanese Unexamined Patent Application Publication No. 2003-57309 (hereafter, referred to as “related art 1”) discloses that, on the LSI pad portion, test-paths, each of which can be used as one of the nodes in a logic circuit, are arranged between the input pad and the output pad in a chip, so that the number of LSIs which can be simultaneously measured is increased without reducing the failure detection rate.
In another approach, a plurality of input pins are bound onto the test board to virtually reduce the number of signals of the LSI (hereafter, referred to as “related art 2”). FIG. 7 shows the related art testing method for the integrated circuit device. As shown in FIG. 7, the LSI 201 has a number of the external pins, then four external pins, namely four input pins 2021-2024 are illustrated in FIG. 7. These input pins 2021-2024 are connected to input buffers 2031-2034 respectively. Four signal lines 2041-2044 which are to be inputted to the input pins 2021-2024 are bound into one signal line 206 on the test board 205. The test pin of the LSI tester is connected to this signal line 206 and the test signal is supplied.
It has been discovered that there is a problem with the related art 1 that a connection test of the internal circuit cannot be performed by inputting the desired test signals from each input pad, because the pad portion of the LSI is handled as one of the nodes in the logic circuit. On the other hand, there is also a problem with the related art 2, where one test signal is supplied from the bound signal lines on the test board. That is, the signal lines are externally bound into one line so that only the same value can be supplied to the input pins, thus a satisfying function test of the LSI would not be performed.